1. Field of the Invention
The present invention relates to a display device and a method of driving the display device.
2. Description of the Prior Art
With the development of information society, various types of requirements for a display device for displaying an image are increasing and, recently, various display devices, such as a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), and an Organic Light Emitting Diode Display Device (OLED), are being used.
Among those display devices, a Liquid Crystal Display (LCD) device includes an array substrate including a thin film transistor, which is a switching device for controlling the on/off of each pixel area, an upper substrate including color filters and/or black matrixes, a display panel including a liquid crystal layer formed between the array substrate and the upper substrate, and a driving unit for controlling the thin film transistor. In an LCD device, alignment of the liquid crystal layer is controlled according to an electric field applied between a common voltage (Vcom) electrode and a pixel (PXL) electrode provided at a pixel area, so as to adjust the permeability of light, and thereby, form an image.
Such a liquid crystal display device drives a liquid crystal panel in an inversion system in order to prevent deterioration of the liquid crystal and to improve the display quality. For the inversion system, a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, or the like has been used.
The frame inversion system, the line inversion system, and the column inversion system, among the inversion driving systems, are capable of reducing electric power consumption as compared to the dot inversion system. However, they have problems in that a crosstalk phenomenon is caused, or a luminance difference occurs between an upper portion and a lower portion of the liquid crystal panel, thereby deteriorating a quality of an image. On the other hand, in the case of the dot inversion system, the deterioration of the image quality may be reduced, so that the dot inversion system may provide an image with an excellent quality as compared with the frame inversion, the line inversion and the column inversion systems. However, the dot inversion system has a problem in that it consumes a larger amount of electric power than an electric power consumption of the line inversion system or the column inversion system.
In order to improve the problems in the above-mentioned systems, a Z-inversion system has been proposed. The Z-inversion system supplies a data voltage to data lines in which pixel electrodes p and a transistors alternate on a left side and a right side, and are arranged, by the column inversion system. That is, the Z-inversion system is a type of an improved column inversion system, in which a circuit is driven by the column inversion system and a transistor of the liquid panel is arranged in an opposite direction in each line so as to implement a display in an identical manner to the dot inversion system. In other words, the Z-inversion system has a similar effect to the dot inversion system in quality of the image, and uses the column inversion system for data. Accordingly, the Z-inversion system provides an excellent quality of the image, and reduces power consumption.
FIG. 1 is a view schematically illustrating a configuration of a pixel in a Z-inversion system.
Referring to FIG. 1, pixels are defined by an intersection of a plurality of gate lines GL1, GL2, GL3, GL4 and GL5 and a plurality of data lines DL1, DL2, DL3, DL4 and DL5, in which the pixels alternate on the left side and the right side, and are connected to data lines respectively. Particularly, a transistor is located at each pixel of the data lines in such a manner that a source electrode (or a drain electrode) of the transistor alternates on the left side and the right side of the data lines and is connected to the data lines.
Referring to FIG. 1, a data voltage with a positive polarity (+) is supplied to data lines DL1, DL3 and DL5 in odd columns, and a data voltage with a negative polarity (−) is supplied to data lines DL2 and DL4 in even columns. Since the transistors of each pixel alternates between the left side and the right side of the data lines and is connected to the data lines, when the data voltage of a specific polarity is supplied to one data line, the data voltage is supplied to the pixels on the left side and the right side of the data line. FIG. 2 is a view illustrating a magnitude of a gate voltage supplied to a second gate line GL2.
Referring to part (A) of FIG. 2, a source electrode 214 of a first transistor located at the first pixel 210 is connected to the first data line DL1, and the source electrode 224 of the second transistor 222 is connected to the second data line DL2. As described above, in the Z inversion system, since a data voltage with a different polarity is supplied to each data line, a data voltage, for example, 5V, of the positive polarity (+) is supplied to a source electrode 214 of a first transistor 212 connected to the first data line DL1, and a data voltage, for example, −5V, of the negative polarity (−) is supplied to a source electrode 224 of a second transistor 222 connected to the second data line DL2.
On the other hand, the gate electrode 216 of the first transistor 212 and the gate electrode 226 of the second transistor 222 share gate line GL2. Therefore, the gate voltage supplied to the second gate line GL2 has to turn on or off both the first transistor 212 and the second transistor 222. Since the data voltage supplied to the source electrode 214 of the first transistor 212 and the data voltage supplied to the source electrode 224 of the second transistor 222 have different polarities, however, the gate voltage supplied to the second gate line GL2 has to turn on or off all transistors supplied with data voltages having different polarities.
Part (B) of FIG. 2 is a view illustrating a waveform of the gate voltage, which is capable of turning on or off the first transistor 212 and the second transistor 222.
According to a characteristic of the transistor, a VGS voltage (a voltage between the gate electrode and the source electrode, or a voltage between the gate electrode and the drain electrode), which turns on or off the transistor is determined. If the VGS voltage turning on the transistor is defined as VGS_ON, and the VGS voltage turning off the transistor is defined as VGS_off, the gate voltage of the second gate line GL2 for turning on both the first transistor 21 and the second transistor 222 has to be a voltage higher than a maximum value VD_P of the data voltage having the positive polarity (+) by VGS_ON. The gate voltage of the second gate line GL2 for turning off both the first transistor 212 and the second transistor 222 has to be a voltage lower than a minimum value VD_N of the data voltage having the negative polarity (1) by VGS_OFF. Accordingly, the gate voltage supplied to the second gate line GL2 has a pulse waveform having a value of (VD_N−VGS_OFF) as a minimum value, and a value of (VD_P+VGS_ON) as a maximum value.
However, there is a problem in that the gate voltage waveform increases consumption of electric power. For example, the gate voltage turning on the second transistor 222 is unnecessarily high. The data voltage of the negative polarity (−) is supplied to the source electrode 224 of the second transistor 222, which has a value between a reference voltage VR and the VD_N. Therefore, it is sufficient that the gate voltage turning on the second transistor 222 is a value of (VR+VGS_ON). Referring to FIG. 2B, since the voltage of (VD_P+VGS_ON) is supplied to the gate voltage for turning on the second transistor 222, an unnecessarily high voltage is supplied. The unnecessary voltage causes an increase of the power consumption.
Since the gate voltage for turning off the first transistor 212 is also unnecessarily low, it causes increased power consumption. The data voltage of the positive polarity (+) is supplied to the source electrode 214 of the second transistor 212, which has a value between a reference voltage VR and VD_P. Therefore, it is sufficient that the gate voltage for turning off the first transistor 212 is a value of (VR−VGS_OFF). Referring to FIG. 2B, since the voltage of (VD_N−VGS_OFF) is supplied as the gate voltage for turning on the second transistor 212, an unnecessarily low voltage is supplied. The unnecessary voltage causes increased power consumption.
Accordingly, increased power consumption in the Z inversion system is a problem.
This problem occurs because an identical gate voltage is supplied to both the transistor supplied with the data voltage of the positive polarity (+) and the transistor supplied with the data voltage of the negative polarity (−).